1. Background Art
In recent years, due to greatly expanded memory capacity and improved performance of processors, resolution of images handled in image processing has been increasing. For example, many application software products handle high definition (HD) video with 1920 horizontal pixels by 1080 vertical pixels. In the future, video with approximately 4000 horizontal pixels by 2000 vertical pixels, or so-called 4K2K video, and video with more pixels will be handled.
Since the processing load of such high-resolution images is heavy, various approaches have been utilized and developed to improve image processing performance. For example, there has been proposed an approach in which a multi-processor system causes each processor to perform processing in parallel. Some approaches are giving attention to improvement of memory access efficiency.
For example, conventionally, there has been known a technology for realizing improvement of memory usage efficiency in a multi-processor system. According to this technology, each processor selects necessary data from among data shared with other processors, duplicates the selected data, and stores it in its own dedicated memory (for example, Patent Literature 1).
Generally, image processing application software stores image data in a synchronous DRAM (SDRAM), and displays images by sequentially reading pieces of the image data that constitute the images, for example.
Here, banks constituting an SDRAM can be accessed by specifying respective row addresses and column addresses therein. By specifying the same row address in the same bank, burst transmission allows for continuous access to pieces of data stored in memory areas specified by column addresses. However, when it is necessary to consecutively access different row addresses in the same bank, there is an interval restriction. According to this restriction, a command needed for each access, i.e., “precharge command” and “activate command”, can be issued only after a certain time period. As a result, memory access efficiency is reduced.
Since the technology described in Patent Literature 1 simply duplicates data and stores the data in a plurality of SDRAMs, the above technology cannot prevent the above-described reduction in memory access efficiency caused by consecutive access to the individual SDRAMs.
As a technology for preventing reduction of memory access efficiency, there has been known a technology for mapping a frame buffer area, which is composed of a plurality of two-dimensional image blocks, to a plurality of SDRAMs, and in particular, for mapping different SDRAMs to adjacent image blocks (for example, see Patent Literature 2).